In order to improve yield in integrated circuit manufacturing, redundant portions of circuitry are frequently included in integrated circuit designs. The redundant circuitry can be used to repair inoperable portions of the integrated circuit under some conditions if certain rerouting steps are taken. In a memory, for example, one or more portions of one or more data storage regions may be inoperable because of defects from semiconductor processing. If redundant circuitry is included in the memory, however, data that would otherwise be stored in the inoperable portion of the array may be rerouted to and from the redundant circuitry.
The redundant circuitry may be local or global. Continuing with the example of memory, if the memory array includes several data regions, local redundant circuitry may be located within each of the data regions, but can only be used to repair inoperable portions in the respective data region where it is located. Global redundant circuitry, on the other hand, may not be located in the data regions, but may be located in a separate, global repair region. As such, the global redundant circuitry can be used to repair inoperable portions of any of a plurality of different data regions. However, if the global repair region has only a single input/output (I/O) bus, only one set of data can be provided to or from the global repair region at a time. If the global repair region includes, for example, 40 columns of redundant data storage circuitry, those redundant columns can be used to repair 40 inoperable columns in a single data region, or in a plurality of different data regions. However, the global repair region can only read from or write to a single column of the global redundant circuitry at a time due to the single I/O bus. Thus, if column 1, for example, is to be read from (or written to) in each of the plurality of data regions at substantially the same time, the use of the global repair region is restricted to repairing column 1 in a single data region by rerouting the logical address of an inoperable portion in that data region to a physical address of redundant circuitry. If the global repair region is used to try to repair the same physical column in a plurality of different data regions, when that column is to be read out, the global repair region would output data from the plurality of different repairs for that column at the same time, thus causing contention on the single I/O bus for the global repair region.
Global repair thus generally works well when the physical locations of the inoperable portions of the integrated circuit are relatively randomly located. In practice, however, integrated circuit defects typically follow a pattern. For example, in a memory array with a plurality of data regions, it is common to have the edge columns of the data regions fail, whereas it is less likely to have inner columns of the data regions fail. In other words, in a memory array with several data regions, defects are likely to occur at similar physical addresses within several of the data regions. These defects may be caused by, for example, breaks in uniformity at the edges of the data regions. In a system with a plurality of data regions where logical addresses are mapped directly to associated physical addresses, global repair cannot be used to repair the same address in more than one data region, as described above.